1. Field of the Invention
This invention generally relates to an apparatus and a method for testing a semiconductor integrated circuit, and, more particularly, to a technique for testing an integrated circuit using probe lines and sense lines, which are incorporated in the integrated circuit so as to intersect (but be electrically separated from) each other.
In general, the known Scan-Path method and the Cross-Check method have been used to test whether a large number of logic elements (e.g., logic gates) incorporated in an integrated circuit function properly or not.
In the Scan-Path method, test pattern signals are applied in sequence to an integrated circuit, and then output pattern signals from the integrated circuit are monitored to detect faulty logic elements.
Recently, the number of logic elements incorporated in integrated circuits has been increasing rapidly due to the continuing progress of integration technology, so that the testing cost of the Scan-Path method has become expensive because testing requires a long time and much labor. In addition, this method requires a large number of flip-flops to be incorporated in the integrated circuit.
U.S. Pat. No. 4,749,947, discloses a technique for testing an integrated circuit by the Cross-Check method. In this testing technique, as shown here in FIG. 15 as an example, a large number of probe lines P.sub.i, P.sub.i+1, P.sub.i+2, each of which corresponds to each row of an array of logic elements such as NAND, NOR, INVERTER, and D-type FLIP-FLOP, and a large number of sense lines S.sub.j, S.sub.j+1, S.sub.j+2, each of which corresponds to each column of an array of logic elements, are incorporated in an integrated circuit so as to intersect at right angles, and each logic element is disposed so as to correspond to one of the intersections where the probe lines P.sub.i, P.sub.i+1, P.sub.i+2 and the sense lines S.sub.j, S.sub.j+1, S.sub.j+2 intersect each other.
A test point TP of each logic element is connected to its corresponding sense line through an electronic or detector switch EQ consisting of a MOSFET, and each detector switch EQ is turned on by applying a selection signal to the corresponding probe line. Therefore, in accordance with the teachings of the above-identified patent, there is provided only one test point TP at each of the intersections between the probe lines P and sense lines S.
For example, with one of a plurality of test pattern signals being applied to the integrated circuit by applying a selection signal of binary state "1" to the probe line P.sub.i, the detector switches EQ .connected to the probe line P.sub.i are turned on, and then test signals at the test points TP of one logic element are fed to the sense lines S.sub.j, S.sub.j+1, S.sub.j+2, respectively. Then, by applying the selection signal to the next probe line P.sub.i+1, test signals at the test points TP of NOR, D-type Flip-Flop, etc., are fed to the sense lines S.sub.j, S.sub.j+1, S.sub.j+2, respectively. In this manner, by applying the selection signal to the probe lines in sequence, all logic elements are tested with regard to the applied one of the plurality of test pattern signals. Then, another test pattern signal is applied to the integrated circuit, and the same steps as above described are carried out, and by applying all the test pattern signals in sequence to the integrated circuit, all logic elements are tested with regard to all test pattern signals.
It is to be noted, however, that the above-described testing technique requires a large number of probe and sense lines to be incorporated in an integrated circuit so that each of the test points corresponds to one of the intersections between the probe and sense lines. In other words, if a matrix structure of logic elements, or a matrix structure of test points, consists of X number of rows and Y number of columns, it is required to incorporate X number of probe lines and Y number of sense lines altogether in an integrated circuit. In order to incorporate such a large number of probe and sense lines, the integration density of an integrated circuit has to be undesirably reduced; therefore, a testing apparatus according to this testing technique can be neither practical nor economical.